Design and optimization of radix-4 booth complex multipliers using CRA and Han-Carlson adders

This research paper's primary goal is to create an effective architecture for a radix-4 complex Vedic multiplier by utilizing the Han-Carlson adder to improve performance and overcome the shortcomings of the current designs. Conventional multipliers are better suited for lower-order bits, while the radix-4 Booth multiplication technique is usually employed for higher-bit-length applications because of its efficiency. In order to create a high-speed multiplier that can efficiently handle high-bit-length operations, this study integrates both strategies. By utilizing the Han-Carlson adder's rapid carry generation capabilities and refining the handling of partial products, the drawbacks of current architectures—such as redundant calculations and additional time caused by intermediate remainders—are lessened. The Virtex-7 device family is the target of the Xilinx software used to implement the suggested design, which shows better speed and performance metrics than earlier approaches.