A Forced Leakage Reduction Technique For Low Power Circuits

Introduction/ Objective: In this study, a Forced Leakage Reduction Technique (FLRT) is proposed to minimize leakage power while preserving correct logic operation. Methods: The detailed simulation has been carried out using the Cadence Virtuoso tool at the 45nm technology node. The SRAM characteristics parameters, such as dynamic power, leakage power, delay, Power-Delay Product (PDP), and stability, are determined for the proposed FLRT structure and for all other reported leakage-reduction techniques, including LECTOR, Sleepy Stack, GALEOR, All NMOS Leakage Feedback with Data Retention (ANLFDR), and Tri-mode Power Gating. All analyses are performed by varying the supply voltages from 0.6V to 1V. To perform a fair comparison, all the techniques are simulated at the same technology node. Results: In the proposed FLRT structure, leakage power is reduced by 2.31×, 2.27×, 1.86×, 2.13×, 2.75×, and 2.31×, respectively, compared to 2-input NAND gate, LECTOR, Sleepy Stack, GALEOR, ANLFDR, and Tri-